Embodiments of the present invention relate to the field of programmable logic devices. Specifically, embodiments of the present invention relate to a system and method for identifying the addresses of configuration cells in a schematic hierarchy.
Integrated circuits, such as, for example, complex programmable logic devices (CPLD) comprise a large number and variety of programmable circuits. By selectively choosing which of the circuits on the CPLD are used and how the circuits are interconnected, a CPLD may be used to implement a wide range of custom circuit designs. Devices such as CPLDs have one or more arrays (e.g., configuration blocks) of memory cells (e.g., configuration bits) that configure the CPLD""s functionality. Each of the memory cells (configuration bits) has an address which may be specified by a word-line and a bit-line. The configuration blocks are programmed at start-up by storing values into the configuration bits. The addresses of the configuration bits must also be determined for simulation. Due to the large number of configuration cells, the process of programming the configuration bits may be complex and problematic for complex PLDs.
In one conventional method, the memory cells (configuration bits) and their associated word-lines and bit-lines are identified manually, and the result would be specific to only one simulator. A separate computer program is written for each programmable logic device circuit design. Therefore, great care must be taken to avoid computer programming errors when using this cumbersome and tedious conventional method. Furthermore, each time the programmable logic device circuit design is changed, the program which identifies the memory cells and their associated word-lines and bit-lines must be changed, by once again manually identifying the wordline and bitline addresses of the configuration bits. Configuration bit errors due to manual entry mistakes may appear as circuit errors, thereby adding to the complexity and difficulty of circuit simulation.
As the complexity of devices such as CPLDs increases, the number of memory cells (configuration bits) increases. Consequently, the risk of error increases when using a conventional manual method for address determination. Furthermore, as separate programs need to be written for each programmable logic device design change, the time spent programming increases dramatically. Clearly, this could delay getting a new product to market and increase design and test costs.
Therefore, it would be advantageous to provide a method and system for automatically identifying configuration circuit addresses in a schematic hierarchy. A method and system are needed which automatically build a data structure comprising configuration circuit addresses from a programmable logic device design. A further needs exists for a such method and system which may easily update the output data structure when changes are made to the input schematic database. A still further need exists for such method and system which avoids the need for custom computer programs for each design and may function across a wide spectrum of applications.
Embodiments of the present invention provide a method and system for automatically identifying configuration cell (circuit) addresses in a schematic hierarchy of a programmable logic device design. Embodiments of the present invention provide for a method and system which automatically builds a data structure comprising configuration circuit addresses, thus minimizing errors which may occur in a manual process. Embodiments of the present invention automatically update the output data structure when changes are made to the input database. Embodiments of the present invention are applicable to a wide range of applications including simulations and testings and avoid the need for custom computer code for each programmable logic device design. Embodiments of the present invention provide these advantages and others not specifically mentioned above but described in the sections to follow.
A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.
In one embodiment, the memory cell is at the lowest level in the schematic hierarchy. In another embodiment, the schematic hierarchy represents a complex programmable logic device (CPLD) design.
In another embodiment, in addition to the above steps, instance names in the hierarchical schematic are sorted alphanumerically. In yet another embodiment, in addition to the above steps, numerical indexes associated with logical names in the hierarchical schematic are renumbered.
In still another embodiment of the present invention, the wordlines and bitlines which are connected to a memory cell (e.g., a configuration bit) are traced to the corresponding wordlines and bitlines of a higher level cell in the schematic hierarchy.